This invention relates to integrated circuit (IC) chip packaging techniques and more particularly to an improved process for packaging flip chip ICs so as to provide a reliable, low thermal resistance enclosure.
High performance processor ICs tend to have a very high input/output (IO) count. Hence, use of area array pads and "flip chip" interconnects becomes a necessity. Flip chip interconnections are used for IC chips having a number of I/O pads too large to be arranged along the chip edges. Instead, the I/O pads are arranged in an array on the chip. Such array precludes connection to the I/O pads by wire bonding or tape automated bonding. Instead, solder bumps are formed on the pads, and the chip is inverted (flipped over) and the I/O pads are soldered to a matching array on a substrate with multi-layer routing, by reflowing the solder bumps. Thus, the chip backside is exposed on top of the subassembly. The space around the electrical connections between the chip and the substrate is typically filled with an insulating resin, called the underfill, to increase the life of the connections.
This construction causes complications, however, in providing a suitable thermal solution, as compared with traditional wire bond interconnection techniques in which the backside of the die or chip is typically connected to a heat spreader. In the case of flip chip interconnects, the thermal spreader also has to be used as a protective lid, requiring attachment of the lid to a substrate at the same time that the thermal interface between the chip and the spreader is formed.
Furthermore, the high performance of state of the art chips, such as ULSI microprocessor ICs, also requires high thermal dissipation (typically in excess of 25 watts). Cooling of such chips when installed and operating, is typically done by air cooling, or by liquid cooling. In the latter case, the liquid cooling subsystem must ordinarily be self-contained to be usable in a desktop workstation. To provide effective cooling to these ICs, an extended surface, or cooling device, needs to be attached to the thermal spreader attached to the back of the flip chip. Such devices can apply mechanical loads to the chip which can damage it.
Prior art packaging techniques strive to avoid exerting undue mechanical loads to the chip by providing the thermal spreader in the form of a lid which is attached to the chip backside and to the ceramic substrate. The lid has a rim which is sized to mechanically contact the opposing face of the surrounding substrate, to which the rim is attached, while providing a clearance between the lid and the chip backside. Sufficient die attach material is laid on the chip backside to fill the space between the chip and the lid. One problem with this approach is that the variation in the clearance between the chip and the lid ceiling is the sum of the variations in the lid depth, the chip thickness and the height of the solder bumps. This variation in clearance, in turn, translates into a variation in thickness of the die attach material and therefore the thermal resistance of the die attach layer, thus rendering the thermal performance of such packaging uncertain.
For a successful thermal solution for high power flip chips, both thermal performance and reliability requirements need to be met. To meet thermal performance requirements, the lid is conventionally made of a high conductivity material. For reliability, it is desirable to have a hermetic or semi-hermetic seal enclosing the chip between the lid and surrounding substrate. One conventional technique is to use an aluminum lid mechanically contacting the surrounding substrate with a silicone adhesive seal. Another approach, typically used in military applications, requiring a hermetic seal is to form the lid of KOVAR iron-nickel alloy and brazing the rim of the lid onto the substrate surface. This approach is both difficult and expensive. Other packaging techniques have used epoxy to attach the lid rings to the substrate in low power, low cost applications.
In order to meet high thermal performance and reliability requirements, a packaging technique must be able to handle high thermal dissipation, typically in excess of 40 watts, preferably from 40 watts to as high as 60 watts (for an ambient temperature of 55.degree. C. and junction temperature of 110.degree. C.), which requires that the materials used for a packaging remain stable for long durations at elevated temperatures.
None of the prior art techniques for packaging flip chip integrated circuits meets the foregoing combination of requirements. Accordingly, a need remains for a flip chip IC packaging technique that provides low thermal resistance, consistency in fabrication and reliability in operation at a reasonable cost.